(1) Field of the Invention
The present invention relates to an operational amplifier, and more particularly to an operational amplifier in which the operation thereof is stopped in response to a control signal and an output terminal thereof is rendered to a high impedance state.
(2) Description of the Related Art
The basic operation of the operational amplifier is to differentially amplify the signal inputted from an inversion input terminal and a non-inversion input terminal and to output the signal thus amplified to an output terminal. There is a prior art operational amplifier in which an additional control signal input terminal is provided and, by stopping the operation in response to the control signal inputted to the additional control signal input terminal, the power consumption is saved during the non-operation state. Such a prior art amplifier is proposed in Japanese Patent Application Kokai Publication No. Sho 63-157513. The circuit configuration and the operation of the proposed amplifier are hereinafter explained.
FIG. 1 shows a circuit diagram of the prior art operational amplifier constituted by CMOS transistors. In the drawings, the numeral 1 represents a control signal input terminal, 2 represents an inversion input terminal, 3 represents a non-inversion input terminal, and 4 represents an output terminal. This operational amplifier 4000 performs a normal operation (hereinafter referred to as an "active state") when a control signal (logical level) inputted to the control signal input terminal 1 is at the low level, and stops its operation (hereinafter referred to as an "inactive state") when the control signal inputted is at the high level. Thus, the explanation is made hereunder by dividing the operation into the two states, namely, one when the control signal is at the low level and the other when the same is at the high level.
First, when the control signal is at the low level, that is, the operational amplifier is in an active state, the N-channel MOS transistor (hereinafter referred to as "N-MOS") 18 turns ON and the N-MOS 19 turns OFF, so that a current flows to a bias section which is formed by a diode connected P-channel MOS transistor (hereinafter referred to as "P-MOS") 17 and an N-MOS 20, and accordingly the bias voltage is supplied to the gates of N-MOSs 21 and 27. Consequently, a constant current is supplied to a differential amplifier constituted by P-MOSs 22 and 23 and N-MOSs 21, 24 and 25, and a voltage which corresponds to the levels of the input signals supplied to the inversion input terminal 2 and the non-inversion input terminal 3 appears at a node 53. On the other hand, since a P-MOS 28 and an N-MOS 34 turn OFF and a P-MOS 32 is ON, a signal which corresponds to the voltage level at the node 53 is outputted from the output terminal 4 through a first output circuit constituted by a P-MOS 26 and an N-MOS 27, a second output circuit constituted by a P-MOS 29 and an N-MOS 30, a third output circuit constituted by a P-MOS 31 and an N-MOS 33, a fourth output circuit constituted by a P-MOS 35 and an N-MOS 36, and a fifth output circuit constituted by a P-MOS 37 and an N-MOS 38. Here, if the potential at the inversion input terminal 2 is lower than that at the non-inversion input terminal 3, the output terminal 4 is coupled to the power source terminal 5 through the P-MOS 37 and, if the potential at the inversion input terminal 2 is higher than that at the non-inversion input terminal 3, the output terminal 4 is coupled to the ground terminal 6 through the N-MOS 38. However, under the normal use state, a negative feedback circuit is often formed between the output terminal 4 and the inversion input terminal 2 so that, at the output terminal 4, there appears a voltage corresponding to levels of the signals supplied to the inversion input terminal 2 and the non-inversion input terminal 3 without the output terminal 4 being saturated to the power source potential or the ground potential.
Next, the operation in the case where the logical level of the control signal is at the high level, that is, in an inactive state, is explained. When the control signal is at the high level, the N-MOS 34 is ON so that the node 51 is grounded. Consequently, the P-MOS 35 turns ON and the P-MOS 37 turns OFF. That is, the output terminal 4 is electrically separated from the power source terminal 5. Also, since the P-MOS 28 becomes ON, the node 49 turns to the power source potential so that the N-MOS 30 becomes ON and the N-MOS 38 becomes OFF. That is, the output terminal 4 is also electrically separated from the ground terminal 6. In this way, the P-MOS 37 and the N-MOS 38 which constitute the fifth output circuit are both OFF so that the output terminal 4 turns to a high impedance state. At this time, since the node 50 is grounded, the P-MOS 31 is turned ON. However, since the P-MOS 32 is turned OFF, there is no possibility for the through-current to flow from the power source terminal 5 to the ground terminal 6 via the P-MOS 31 and the N-MOS 34. On the other hand, the bias section stops its operation because the node 48 is grounded as the N-MOS 19 is ON. Consequently, the N-MOSs 21 and 27 do not allow the current to flow no matter what signals are supplied to the inversion input terminal 2 and the non-inversion input terminal 3 and, since the N-MOS 18 becomes OFF, the bias section turns to a complete cut-off state. In this way, in the inactive state, irrespective of the levels of the signals supplied to the inversion input terminal 2 and the non-inversion input terminal 3, the output terminal 4 turns to a high impedance state, so that it is electrically separated from the next stage circuit connected thereto, and all the current paths from the power source terminal 5 to the ground terminal 6 are cut-off, whereby the power consumption is rendered to almost zero.
Next, with reference to a timing chart of FIG. 2, explanation is made on the operation of the operational amplifier 4000 before and after the change to take place in the control signal supplied to the control signal input terminal 1. First, when the control signal is at the low level (time period T10), that is, in an active state, the nodes 49 and 51 and the output terminal 4 are of the potential corresponding to the levels of the input signals supplied to the inversion input terminal 2 and the non-inversion input terminal 3. Subsequently, at the timing t13, when the control signal supplied to the control signal input terminal 1 changes to the high level, the internal control signals 201 and 202 are inverted accordingly. However, since the internal control signal 202 is a signal having passed through the inverter 200, the time when this is inverted is delayed from the time when the internal control signal 201 is inverted as shown in FIG. 2. As a consequence, the node 51 is grounded before the node 49 rises to the power source potential so that, between the P-MOS 37 and the N-MOS 38, it is the P-MOS 37 that turns OFF first. At this time, the N-MOS 38 is still conductive in accordance with the level of the input signal so that the output terminal 4 turns to a high impedance state after the potential thereat having once fallen to the ground potential. Then, while the control signal is at the high level (inactive state), the state of high impedance continues (time period T11). When the control signal again changes to the low level at the timing t14, the internal control signals 201 and 202 are inverted, but the time when the internal control signal 202 is inverted is delayed because of the presence of the inverter 200 as explained above. As a consequence, while the node 49 remains at the power source potential, that is, the P-MOS 31 is remaining as being ON, the N-MOS 32 first turns ON and, moreover, since the N-MOS 34 turns OFF, the potential at the node 51 rises to the power source potential. Consequently, the potential at the node 52 becomes the ground potential and the P-MOS 37 turns ON accordingly, but the N-MOS 38 is still OFF. That is, at the timing t14, irrespective of the levels of the input signals, the P-MOS 37 turns ON while the N-MOS 38 is still in the OFF state. Thus, as shown in FIG. 2, the potential at the output terminal 4 once rises to the power source potential. Subsequently, the P-MOS 28 turns OFF and, since the potential at the node 49 becomes a potential that corresponds to the input signal, the potential at the output terminal 4 becomes a potential that corresponds to the input signal accordingly.
The conventional operational amplifier explained above operates such that the potential at the output terminal 4 once falls to the ground potential when the change takes place from the active state to the inactive state in accordance with the change of the control signal supplied to the control signal input terminal 1 and, inversely, once rises to the power source potential when the change takes place from the inactive state to the active state. Thus, irrespective of the levels of the input signals supplied to the inversion input terminal 2 and the non-inversion input terminal 3, the next stage circuit connected to the output terminal 4 receives the low level signal every time the operational amplifier 4000 turns to the inactive state and receives a high level signal every time the operational amplifier 4000 turns to the active state. This can be a cause for the occurrence of malfunctions in the next stage circuit.
For the above reason, it is necessary that the next stage circuit be constructed so as to avoid the occurrence of malfunctions caused by changes in the output signals from the operational amplifier. However, in the conventional operational amplifier 4000, the signal transiently outputted from the output terminal 4 when the state changes to the inactive state and that transiently outputted when the state changes to the active state are different from each other as explained above. That is, when the change is to the inactive state, the output terminal 4 outputs a low level signal and, when the change is to the active state, the output terminal 4 outputs a high level signal. Thus, the next stage circuit that receives the above signals must be provided with some additional means in order to ensure the avoidance of the malfunctioning.
The problem in the above conventional amplifier circuit is that, when the changes takes place from the inactive state to the active state, the potential of the output terminal 4 at the timing t14 in FIG. 2 once changes from the ground potential to the power source potential followed by a change to the potential (potential "A") that corresponds to levels of the input signals supplied to the inversion input terminal 2 and the non-inversion input terminal 3. Thus, in the next stage circuit, the inputs are in the sequence of 1) ground potential, 2) power source potential, and 3) potential "A". An example of the specific means that may be additionally employed in order to avoid the above problem is an analog switch which may be provided between the output terminal 4 and an input terminal of the next stage circuit of the conventional circuit so that the portion of the above change to the potential "A" has not effect on the operation.
On the other hand, according to the present invention, whether the change is from the active state to the inactive state or from the inactive state to the active state, the change is only between the potential "A" and the ground potential, and this makes the operation of the circuit according to the present invention distinctly different from that in the prior art.